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MCP6141/2/3/4
600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps
Features:
* * * * * * * * * Low Quiescent Current: 600 nA/amplifier (typical) Gain Bandwidth Product: 100 kHz (typical) Stable for gains of 10 V/V or higher Rail-to-Rail Input/Output Wide Supply Voltage Range: 1.4V to 6.0V Available in Single, Dual, and Quad Chip Select (CS) with MCP6143 Available in 5-lead and 6-lead SOT-23 Packages Temperature Ranges: - Industrial: -40C to +85C - Extended: -40C to +125C
Description:
The MCP6141/2/3/4 family of non-unity gain stable operational amplifiers (op amps) from Microchip Technology Inc. operate with a single supply voltage as low as 1.4V, while drawing less than 1 A (maximum) of quiescent current per amplifier. These devices are also designed to support rail-to-rail input and output operation. This combination of features supports battery-powered and portable applications. The MCP6141/2/3/4 amplifiers have a gain bandwidth product of 100 kHz (typical) and are stable for gains of 10 V/V or higher. These specifications make these op amps appropriate for battery powered applications where a higher frequency response from the amplifier is required. The MCP6141/2/3/4 family operational amplifiers are offered in single (MCP6141), single with Chip Select (CS) (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. The MCP6141 device is available in the 5-lead SOT-23 package, and the MCP6143 device is available in the 6-lead SOT-23 package.
Applications:
* * * * Toll Booth Tags Wearable Products Temperature Measurement Battery Powered
Design Aids:
* * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Simulation Tool Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes
Package Types
MCP6141 PDIP, SOIC, MSOP
NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC
MCP6143 PDIP, SOIC, MSOP
NC 1 VIN- 2 VIN+ 3 VSS 4 8 CS 7 VDD 6 VOUT 5 NC
Related Devices:
* MCP6041/2/3/4: Unity Gain Stable Op Amps
MCP6141 SOT-23-5
VOUT 1 VSS 2 VIN+ 3 4 VIN- 5 VDD
MCP6143 SOT-23-6
VOUT 1 VSS 2 VIN+ 3 6 VDD 5 CS 4 VIN-
Typical Application
R1 V1 R2 V2 R3 V3 MCP614X VREF Inverting, Summing Amplifier RF VOUT
MCP6142 PDIP, SOIC, MSOP
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD
MCP6144 PDIP, SOIC, TSSOP
VOUTA 1 14 VOUTD 13 VIND- 12 VIND+ 11 VSS 10 VINC+ 9 VINC- 8 VOUTC
7 VOUTB VINA- 2 6 VINB- VINA+ 3 5 VINB+ VDD 4 VINB+ 5 VINB- 6 VOUTB 7
(c) 2009 Microchip Technology Inc.
DS21668D-page 1
MCP6141/2/3/4
NOTES:
DS21668D-page 2
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage and Current Limits".
Absolute Maximum Ratings
VDD - VSS ........................................................................7.0V Current at Analog Input Pins .........................................2 mA Analog Inputs (VIN+, VIN-) ........ VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature ................................... -65C to +150C Maximum Junction Temperature (TJ)......................... .+150C ESD Protection On All Pins (HBM; MM) .............. 4 kV; 400V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Input Offset Input Offset Voltage Drift with Temperature
Sym
VOS VOS/TA VOS/TA
Min
-3 -- -- 70 -- -- -- -- -- -- VSS-0.3 62 60 60 95
Typ
-- 1.8 10 85 1 20 1200 1 10 ||6 1013||6 -- 80 75 80 115
13
Max
+3 -- -- -- -- 100 5000 -- -- -- VDD+0.3 -- -- -- --
Units
mV V/C V/C dB pA pA pA pA ||pF ||pF V dB dB dB dB
Conditions
VCM = VSS VCM = VSS, TA= -40C to +85C VCM = VSS, TA = +85C to +125C VCM = VSS
Power Supply Rejection Input Bias Current and Impedance Input Bias Current Industrial Temperature Extended Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common-Mode Input Range Common-Mode Rejection Ratio
PSRR IB IB IB IOS ZCM ZDIFF VCMR CMRR CMRR CMRR
TA = +85 TA = +125
VDD = 5V, VCM = -0.3V to 5.3V VDD = 5V, VCM = 2.5V to 5.3V VDD = 5V, VCM = -0.3V to 2.5V RL = 50 k to VL, VOUT = 0.1V to VDD-0.1V RL = 50 k to VL, 0.5V input overdrive RL = 50 k to VL, AOL 95 dB VDD = 1.4V VDD = 5.5V Note 1 IO = 0
Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Linear Region Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier VDD IQ 1.4 0.3 -- 0.6 6.0 1.0 V A VOL, VOH VOVR ISC ISC VSS + 10 VSS + 100 -- -- -- -- 2 20 VDD - 10 VDD - 100 -- -- mV mV mA mA AOL
Note 1:
All parts with date codes February 2008 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V
(c) 2009 Microchip Technology Inc.
DS21668D-page 3
MCP6141/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
AC Response Gain Bandwidth Product Slew Rate Phase Margin Noise Input Voltage Noise Input Voltage Noise Density Input Current Noise Density
Sym
GBWP SR PM Eni eni ini
Min
-- -- -- -- -- --
Typ
100 24 60 5.0 170 0.6
Max
-- -- -- -- -- --
Units
kHz V/ms VP-P G = +10 V/V
Conditions
f = 0.1 Hz to 10 Hz
nV/Hz f = 1 kHz fA/Hz f = 1 kHz
MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters
CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High CS Input High, GND Current Amplifier Output Leakage, CS High Dynamic Specifications CS Low to Amplifier Output Turn-on Time CS High to Amplifier Output High-Z Hysteresis
Sym
Min
Typ
Max
Units
Conditions
VIL ICSL VIH ICSH ISS IOLEAK tON tOFF VHYST
VSS --
-- 5
VSS+0.3 --
V pA CS = VSS
VDD-0.3 -- -- --
-- 5 -20 20
VDD -- -- --
V pA pA pA CS = VDD CS = VDD CS = VDD G = +1 V/V, CS = 0.3V to VOUT = 0.9VDD/2 G = +1 V/V, CS = VDD-0.3V to VOUT = 0.1VDD/2 VDD = 5.0V
-- -- --
2 10 0.6
50 -- --
ms s V
CS
VIL tON
VIH tOFF High-Z -0.6 A (typical)
VOUT High-Z ISS -20 pA (typical) ICS 5 pA (typical)
-20 pA (typical) 5 pA (typical)
FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only).
DS21668D-page 4
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 256 230 206 85 163 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA TA -40 -40 -40 -65 -- -- -- -- +85 +125 +125 +150 C C C C Industrial Temperature parts Extended Temperature parts (Note 1) Sym. Min. Typ. Max. Units Conditions
The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C.
1.1
Test Circuits
The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 "Supply Bypass". VDD RN 0.1 F 1 F VOUT CL VDD/2 RG RF VL RL
VIN
MCP614X
FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.
VDD RN 0.1 F 1 F VOUT CL VIN RG RF VL RL
VDD/2
MCP614X
FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.
(c) 2009 Microchip Technology Inc.
DS21668D-page 5
MCP6141/2/3/4
NOTES:
DS21668D-page 6
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0%
Percentage of Occurrences
-3
-2
-1 0 1 Input Offset Voltage (mV)
2
3
Percentage of Occurrences
2396 Samples VCM = VSS
12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% -10 -8
234 Samples Representative Lot VDD = 1.4V VCM = VSS TA = +85C to +125C
-6 -4 -2 0 2 4 6 8 Input Offset Voltage Drift (V/C)
10
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Input Offset Voltage Drift with TA = +85C to +125C and VDD = 1.4V.
16% Percentage of Occurrences
234 Samples Representative Lot VDD = 5.5V VCM = VSS TA = +85C to +125C
12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0%
Percentage of Occurrences
2267 Samples TA = -40C to +85C VCM = VSS
14% 12% 10% 8% 6% 4% 2% 0% -10 -8
-10
-8
-6 -4 -2 0 2 4 6 Input Offset Voltage Drift (V/C)
8
10
-6 -4 -2 0 2 4 6 8 Input Offset Voltage Drift (V/C)
10
FIGURE 2-2: Input Offset Voltage Drift with TA = -40C to +85C.
1000 800 600 400 200 0 -200 -400 -600 -800 -1000
FIGURE 2-5: Input Offset Voltage Drift with TA = +85C to +125C and VDD = 5.5V.
1000 800 600 400 200 0 -200 -400 -600 -800 -1000
Input Offset Voltage (V)
VDD = 1.4V TA = +125C TA = +85C
Input Offset Voltage (V)
VDD = 5.5V TA = +125C TA = +85C
TA = +25C TA = -40C
TA = +25C TA = -40C
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V.
FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V.
(c) 2009 Microchip Technology Inc.
DS21668D-page 7
6.0
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
500 Input Offset Voltage (V) 450 400 350 300 250 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
VDD = 1.4V
6 Input, Output Voltages (V) 5 4 3 2 1 0 -1 0
VDD = 5.0V G = +11 V/V
VIN
VDD = 5.5V
VOUT
5
Time (5 ms/div) 10 15
20
25
FIGURE 2-7: Output Voltage.
1,000 Input Noise Voltage Density (nV/Hz)
Input Offset Voltage vs.
FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal.
300 250 200 150 100 50 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) 5.5
Input Noise Voltage Density (nV/Hz)
f = 1 kHz VDD = 5.0V
100 0.1 1 10 100 Frequency (Hz) 1000
FIGURE 2-8: vs. Frequency.
100 90 CMRR, PSRR (dB) 80 70 60 50 40 30 20 1 1
Referred to Input
Input Noise Voltage Density
FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage.
100 95 PSRR, CMRR (dB) 90 85 80 75 70
CMRR (VDD = 5.0V, VCM = -0.3V to +5.3V) PSRR (VCM = VSS)
PSRR- PSRR+ CMRR
10 10
100 1k 100 1,000 Frequency (Hz)
10k 10,000
-50
-25
0 25 50 75 100 Ambient Temperature (C)
125
FIGURE 2-9: Frequency.
CMRR, PSRR vs.
FIGURE 2-12: Temperature.
CMRR, PSRR vs. Ambient
DS21668D-page 8
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
Input Bias and Offset Currents (pA) 10k 10000 1k 1000 100 10 1 1 0.1 0.1 45 55 65 75 85 95 105 Ambient Temperature (C) 115 125
| IOS |
Input Bias, Offset Currents (pA)
VDD = 5.5V VCM = VDD
10000 10k 1k 1000 100 10 1 0.1 0.1
TA = +125C
VDD = 5.5V
IB
IB
TA = +85C
| IOS |
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V)
FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature.
120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20
Gain Phase
FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage.
130 DC Open-Loop Gain (dB)
0 -30 -60 -90 -120 -150 -180 -210 Open-Loop Phase ()
120 110 100 90 80 70 60 100 1.E+02
VOUT = 0.1V to VDD - 0.1V VDD = 1.4V VDD = 5.5V
-40 -240 0.01 1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 100k 1 10 100 1k 10k 1.E+ 1.E- 0.1 02 01 00 Frequency (Hz)03 01 02 04 05
1k 10k 1.E+03 1.E+04 Load Resistance ()
100k 1.E+05
FIGURE 2-14: Frequency.
140
Open-Loop Gain, Phase vs.
FIGURE 2-17: Load Resistance.
140 DC Open-Loop Gain (dB) 130 120 110 100 90 80 70 0.00
DC Open-Loop Gain vs.
DC Open-Loop Gain (dB)
RL = 50 k VDD = 5.5V
130 120 110 100 90 80 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 5.5
RL = 50 k VOUT = 0.1V to VDD - 0.1V
VDD = 1.4V
0.05 0.10 0.15 0.20 Output Voltage Headroom; VDD - VOH or VOL - VSS (V)
0.25
FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage.
FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom.
(c) 2009 Microchip Technology Inc.
DS21668D-page 9
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
140 Channel-to-Channel Separation (dB) 130 120 110 100 90
Input Referred
80 1k 1.E+03
120 110 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 -0.5
PM (G = +10)
VDD = 5.0V
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency (Hz)
10k 1.E+04
Common Mode Input Voltage
FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only).
90 Gain Bandwidth Product (kHz) 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 Ambient Temperature (C)
VDD = 1.4V GBWP
FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage.
Gain Bandwidth Product (kHz)
PM (G = +10)
90 80 Phase Margin () 70 60 50 40 30 20 10 0 125
90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 Ambient Temperature (C)
VDD = 5.5V PM (G = +10) GBWP
5.5 90 80 60 50 40 30 20 10 0 125 Phase Margin () 70
FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V.
0.8 0.7 Quiescent Current (A/Amplifier) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
TA = +125C TA = +85C TA = +25C TA = -40C
FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V.
35 Output Short Circuit Current Magnitude (mA) 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (C)
TA = -40C TA = +25C TA = +85C TA = +125C
FIGURE 2-21: Quiescent Current vs. Power Supply Voltage.
FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage.
DS21668D-page 10
(c) 2009 Microchip Technology Inc.
Phase Margin ()
GBWP
120 110 100 90 80 70 60 50 40 30 20 10 0
Gain Bandwidth Product (kHz)
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
1000 Output Voltage Headroom; VDD - V OH or V OL - V SS (mV)
100
VDD - VOH
10
VOL - VSS
1 0.01
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Output Voltage Headroom, VDD - V OH or V OL - V SS (mV)
VDD = 5.5V RL = 50 k VOL - VSS
VDD - VOH
0.1 1 Output Current Magnitude (mA)
10
-50
-25
0 25 50 75 100 Ambient Temperature (C)
125
FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude.
40 35 Slew Rate (V/ms) 30 25 20 15 10 5 0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 1.4V Low-to-High VDD = 5.5V High-to-Low
FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature.
10 Maximum Output Voltage Swing (VP-P)
VDD = 5.5V
1
VDD = 1.4V
0.1 100 1.E+02
1k 1.E+03 Frequency (Hz)
10k 1.E+04
FIGURE 2-26: Temperature.
80 Output Voltage (20 mV/div) 60 40 20 0
Slew Rate vs. Ambient
FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency.
80 60 Voltage (20 mV/div) 40 20 0
G = +11 V/V RL = 50 k
G = -10 V/V RL = 50 k
-20 -40 -60 -80 0.0 0.1 0.2 0.3 Time (100 s/div) 0.7 0.4 0.5 0.6 0.8 0.9 1.0
-20 -40 -60 -80 0.0 0.1 0.2 0.3 Time (100 s/div) 0.7 0.4 0.5 0.6 0.8 0.9 1.0
FIGURE 2-27: Pulse Response.
Small Signal Non-inverting
FIGURE 2-30: Response.
Small Signal Inverting Pulse
(c) 2009 Microchip Technology Inc.
DS21668D-page 11
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = +25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF, and CS is tied low.
5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0 0 1 Time (200 s/div) 1 1 1 1 2 2 2 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0 0 1 Time (200 s/div) 1 1 1 1 2 2 2
VDD = 5.0V G = +11 V/V RL = 50 k
VDD = 5.0V G = -10 V/V RL = 50 k
FIGURE 2-31: Pulse Response.
25.0 22.5 20.0 17.5 15.0 12.5 CS Voltage (V) 10.0 7.5 5.0 2.5 0.0 0 1 2
CS On
Large Signal Non-inverting
FIGURE 2-34: Response.
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Large Signal Inverting Pulse
On
4.5 Output Voltage (V) 4.0 3.5
Internal CS Switch Output (V)
VDD = 5.0V G = +11 V/V VIN = +3.0V
5.0
VOUT On Hysteresis CS High-to-Low CS Low-to-High VOUT High-Z VDD = 5.0V G = +11 V/V VIN = 3.0V
High-Z
VOUT
3.0 2.5 2.0 1.5 1.0 0.5 0.0
3 Time (1 ms/div)7 456
8
9
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CS Voltage (V)
FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only).
1.E-02 10m 1m 1.E-03 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10
FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only).
Input Current Magnitude (A)
10p 1.E-11 1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
+125C +85C +25C -40C
FIGURE 2-33: Input Current vs. Input Voltage (Below VSS).
DS21668D-page 12
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6141 MSOP, PDIP, SOIC
6 2 3 7 -- -- -- -- -- -- 4 -- -- -- -- 1, 5, 8
PIN FUNCTION TABLE
MCP6142 MSOP, PDIP, SOIC
1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- --
MCP6143 MSOP, PDIP, SOIC
6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 8 1, 5
MCP6144 MSOP, PDIP, SOIC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- --
SOT-23-5
1 4 3 5 -- -- -- -- -- -- 2 -- -- -- -- --
SOT-23-6
1 4 3 6 -- -- -- -- -- -- 2 -- -- -- 5 --
Symbol
Description
VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD CS NC
Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Chip Select No Internal Connection
3.1
Analog Outputs
3.4
Power Supply Pins
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents.
The positive power supply pin (VDD) is 1.4V to 6.0V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors.
3.3
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation.
(c) 2009 Microchip Technology Inc.
DS21668D-page 13
MCP6141/2/3/4
NOTES:
DS21668D-page 14
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6141/2/3/4 family of op amps is manufactured using Microchip's state of the art CMOS process These op amps are stable for gains of 10 V/V and higher. They are suitable for a wide range of general purpose, low power applications. See Microchip's related MCP6041/2/3/4 family of op amps for applications needing unity gain stability. dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 V2 R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > D2 MCP604X VOUT
4.1
4.1.1
Rail-to-Rail Input
PHASE REVERSAL
The MCP6141/2/3/4 op amps are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-10 shows an input voltage exceeding both supplies with no phase inversion.
4.1.2
INPUT VOLTAGE AND CURRENT LIMITS
The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad
FIGURE 4-2: Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-33. Applications that are high impedance may need to limit the usable voltage range.
4.1.3
VIN+ Bond Pad Input Stage Bond V - IN Pad
NORMAL OPERATION
VSS Bond Pad
The input stage of the MCP6141/2/3/4 op amps uses two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. There are two transitions in input behavior as VCM is changed. The first occurs, when VCM is near VSS + 0.4V, and the second occurs when VCM is near VDD - 0.5V (see Figure 2-3 and Figure 2-6). For the best distortion performance with non-inverting gains, avoid these regions of operation.
FIGURE 4-1: Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD, and
(c) 2009 Microchip Technology Inc.
DS21668D-page 15
MCP6141/2/3/4
4.2 Rail-to-Rail Output 4.4
4.4.1
Stability
NOISE GAIN
There are two specifications that describe the output swing capability of the MCP6141/2/3/4 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load condition. Thus, the output voltage swings to within 10 mV of either supply rail with a 50 k load to VDD/2. Figure 2-10 shows how the output voltage is limited when the input goes beyond the linear region of operation. The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Range. This specification defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. To verify linear operation in this range, the large signal DC Open-Loop Gain (AOL) is measured at points inside the supply rails. The measurement must meet the specified AOL condition in the specification table.
The MCP6141/2/3/4 op amp family is designed to give high bandwidth and slew rate for circuits with high noise gain (GN) or signal gain. Low gain applications should be realized using the MCP6041/2/3/4 op amp family; this simplifies design and implementation issues. Noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all other voltage sources are zeroed (shorted out). Noise gain is independent of signal gain and depends only on components in the feedback loop. The amplifier circuits in Figure 4-3 and Figure 4-4 have their noise gain calculated as follows:
EQUATION 4-2:
RF G N = 1 + ------ 10 V/V RG In order for the amplifiers to be stable, the noise gain should meet the specified minimum noise gain. Note that a noise gain of GN = +10 V/V corresponds to a non-inverting signal gain of G = +10 V/V, or to an inverting signal gain of G = -9 V/V. RIN VIN MCP614X RG RF VOUT
4.3
Output Loads and Battery Life
The MCP6141/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This prevents excessive current draw, and reduced battery life, when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 k load resistor will cause the supply current to increase by 25 A, depleting the battery 43 times as fast as IQ (0.6 A, typical) alone. High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 F capacitor at the output presents an AC impedance of 15.9 k (1/2fC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 VP-P sinewave (1.77 Vrms), under these conditions, is:
FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration.
RG VIN RIN MCP614X RF VOUT
EQUATION 4-1:
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL ) = (5V)(0.6 A + 5.0Vp-p * 100Hz * 0.1F) = 3.0 W + 50 W This will drain the battery 18 times as fast as IQ alone.
FIGURE 4-4: Noise Gain for Inverting Gain Configuration.
DS21668D-page 16
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
Figure 4-5 shows three example circuits that are unstable when used with the MCP6141/2/3/4 family. The unity gain buffer and low gain amplifier (non-inverting or inverting) are at gains that are too low for stability (see Equation 4-2).The Miller integrator's capacitor makes it reach unity gain at high frequencies, causing instability. Note: The three circuits shown in Figure 4-5 are not to be used with the MCP6141/2/3/4 op amps. They are included for illustrative purposes only. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +10), a small series resistor at the output (RISO in Figure 4-6) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG VA CL MCP614X Unity Gain Buffer VB RF RISO VOUT
MCP614X VIN Low Gain Amplifier RG V1 RN V2 MCP614X RF
VOUT
FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads.
Figure 4-7 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -9 V/V gives GN = +10 V/V).
100,000 100k Recommended R ISO ()
VOUT
RF 1 + ------ < 10 RG
10k 10,000
GN = +10 GN = +20 GN +50
Miller Integrator R VIN MCP614X C VOUT
1k 1,000 1p 10p 100p 1n 1.E+00 1.E+01 1.E+02 1.E+03 Normalized Load Capacitance; CL/GN (F)
FIGURE 4-7: Recommended RISO Values for Capacitive Loads. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. 4.4.2 CAPACITIVE LOADS
After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6141/2/3/4 SPICE macro model are helpful.
Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior.
4.5
MCP6143 Chip Select
The MCP6143 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 50 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse.
(c) 2009 Microchip Technology Inc.
DS21668D-page 17
MCP6141/2/3/4
4.6 Supply Bypass
Guard Ring VIN- VIN+ With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor is not required for most applications and can be shared with other nearby analog parts.
FIGURE 4-9: for Inverting Gain.
1.
Example Guard Ring Layout
4.7
Unused Op Amps
An unused op amp in a quad package (MCP6144) should be configured as shown in Figure 4-8. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp near its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. 1/4 MCP6144 (A) VDD R1 VDD 1/4 MCP6144 (B) VDD
2.
Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain (convert current to voltage, such as photo detectors) amplifiers: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface.
R R2
10R
VREF
R2 V REF = V DD -------------------R1 + R2
FIGURE 4-8:
Unused Op Amps.
4.8
PCB Surface Leakage
In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6141/2/3/4 family's bias current at +25C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-9.
DS21668D-page 18
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
4.9
4.9.1
Application Circuits
BATTERY CURRENT SENSING
4.9.2
INVERTING SUMMING AMPLIFIER
The MCP6141/2/3/4 op amps' Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current sensing applications. The very low quiescent current (0.6 A, typical) help prolong battery life, and the rail-to-rail output supports detection low currents. Figure 4-10 shows a high side battery current sensor circuit. The 1 k resistor is sized to minimize power losses. The battery current (IDD) through the 1 k resistor causes its top terminal to be more negative than the bottom terminal. This keeps the common mode input voltage of the op amp below VDD, which is within its allowed range. When no current is flowing, the output will be at its Maximum Output Voltage Swing (VOH), which is virtually at VDD.
.
The MCP6141/2/3/4 op amp is well suited for the inverting summing amplifier shown in Figure 4-11 when the resistors at the input (R1, R2, and R3) make the noise gain at least 10 V/V. The output voltage (VOUT) is a weighted sum of the inputs (V1, V2, and V3), and is shifted by the VREF input. The necessary calculations follow in Equation 4-3.
.
R1 V1 R2 V2 R3 V3 MCP614X VREF RF VOUT
IDD 1.4V to 6.0V 1 k MCP6141 VDD
FIGURE 4-11: EQUATION 4-3:
VOUT Noise Gain:
Summing Amplifier.
1- 1- 1G N = 1 + R F ----- + ----- + ----- 10 V/V R R 2 R 3 1 100 k 1 M Signal Gains: G1 = -RF R1 G2 = -RF R2 G3 = -RF R3 Output Signal: V OUT = V 1 G 1 + V 2 G 2 + V 3 G 3 + V REF G N
V OUT = V DD - ( 1 k ) ( 11 V/V )I DD
FIGURE 4-10: Sensor.
High Side Battery Current
(c) 2009 Microchip Technology Inc.
DS21668D-page 19
MCP6141/2/3/4
NOTES:
DS21668D-page 20
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
5.0 DESIGN AIDS
5.5
Microchip provides the basic design tools needed for the MCP6141/2/3/4 family of op amps.
Analog Demonstration and Evaluation Boards
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6141/2/3/4 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Two of our boards that are especially useful are: * 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV * 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV
5.6
Application Notes
5.2
FilterLab(R) Software
Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip.com/appnotes and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 These application notes and others are listed in the design guide: * "Signal Chain Design Guide", DS21825
5.3
MindiTM Simulation Tool
Microchip's MindiTM simulation tool aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online simulation tool available from the Microchip web site at www.microchip.com/mindi. This interactive simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi simulation tool can be downloaded to a personal computer or workstation.
5.4
Microchip Advanced Part Selector (MAPS)
MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts.
(c) 2009 Microchip Technology Inc.
DS21668D-page 21
MCP6141/2/3/4
NOTES:
DS21668D-page 22
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP6141)
Device E-Temp Code ASNN
Example:
XXNN
MCP6141
Note: Applies to 5-Lead SOT-23
AS25
Example:
6-Lead SOT-23 (MCP6143)
Device
E-Temp Code AWNN
XXNN
8-Lead MSOP XXXXXX YWWNNN
MCP6143
Note: Applies to 6-Lead SOT-23
AW25
Example: 6143I 918256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP6141 I/P256 0918 MCP6141 E/P e3 256 0918
OR
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN
Example: MCP6142 I/SN0918 256 MCP6142E SN e3 0918 256
OR
Legend: XX...X Y YY WW NNN * Note:
e3
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
DS21668D-page 23
MCP6141/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6144) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP6144-I/P 0918256
OR
MCP6144 I/P e3 0918256
Example:
14-Lead SOIC (150 mil) (MCP6144)
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP6144ISL 0918256
OR
MCP6144 e3 I/SL^^ 0918256
14-Lead TSSOP (MCP6144)
Example:
XXXXXXXX YYWW NNN
6144ST 0918 256
OR
6144EST 0918 256
DS21668D-page 24
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
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DS21668D-page 32
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
APPENDIX A: REVISION HISTORY
Revision A (September 2002)
* Original Release of this Document.
Revision D (May 2009)
The following is the list of modifications: 1. 2. DC Electrical Charactistics table: Corrected formatting issue in Output section. AC Electrical Characteristics table: Slew Rate - changed typical value from 3.0 to 24. Changed Phase Margin from 65 to 60. Changed Phase Margin Condition from G=+1 to G=+10 V/V. Updated Package Outline Drawings Updated Revision History.
3. 4.
Revision C (December 2007)
* Updated Figures 2.4 and 2.5 * Expanded Analog Input Absolute Max Voltage Range (applies retroactively) * Expanded maximum operating VDD (going forward) * Section 1.0 "Electrical Characteristics" updated * Section 2.0 "Typical Performance Curves" updated * Section 4.0 "Applications Information" - Updated input stage explanation * Section 5.0 "Design Aids" updated
Revision B (November 2005)
The following is the list of modifications: 1. Added the following: a) SOT-23-5 package for the MCP6141 single op amps. b) SOT-23-6 package for the MCP6143 single op amps with Chip Select. c) Extended Temperature (-40C to +125C) op amps. Updated specifications in Section 1.0 "Electrical Characteristics" for E-temp parts. Corrected and updated plots in Section 2.0 "Typical Performance Curves". Added Section 3.0 "Pin Descriptions". Updated Section 4.0 "Applications Information" and added section on unused op amps. Updated Section 5.0 "Design Aids" to include FilterLab. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information in Section 6.0 "Packaging Information". Added Appendix A: "Revision History".
2. 3. 4. 5.
6. 7.
8.
(c) 2009 Microchip Technology Inc.
DS21668D-page 33
MCP6141/2/3/4
NOTES:
DS21668D-page 34
(c) 2009 Microchip Technology Inc.
MCP6141/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. Device
-X Temperature Range
MCP6141: MCP6141T: MCP6142: MCP6142T: MCP6143: MCP6143T: MCP6144: MCP6144T:
/ XX Package
Examples:
a) b) MCP6141-I/P: Industrial Temperature 8 lead PDIP package. MCP6141T-E/OT: Tape and Reel, Extended Temperature 5 lead SOT-23 package.
Device:
Single Op Amp Single Op Amp (Tape and Reel for SOT-23, SOIC, MSOP) Dual Op Amp Dual Op Amp (Tape and Reel for SOIC and MSOP) Single Op Amp w/ CS Single Op Amp w/ CS (Tape and Reel for SOT-23, SOIC, MSOP) Quad Op Amp Quad Op Amp (Tape and Reel for SOIC and TSSOP)
a) b)
MCP6142-I/SN:
Industrial Temperature 8 lead SOIC package. MCP6142T-E/MS: Tape and Reel, Extended Temperature 8 lead MSOP package.
a) b)
Industrial Temperature, 8 lead PDIP package. MCP6143T-E/CH: Tape and Reel, Extended Temperature 6 lead SOT-23 package. MCP6144-I/SL: Industrial Temperature 14 lead PDIP package. MCP6144T-E/ST: Tape and Reel, Extended Temperature 14 lead TSSOP package.
MCP6143-I/P:
a) Temperature Range: I E Package: CH MS OT P SL SN ST = -40C to +85C (industrial) = -40C to +125C (extended) = Plastic Small Outline Transistor (SOT-23), 6-lead (Tape and Reel - MCP6143 only) = Plastic Micro Small Outline (MSOP), 8-lead = Plastic Small Outline Transistor (SOT-23), 5-lead (Tape and Reel - MCP6141 only) = Plastic DIP (300 mil body), 8-lead, 14-lead = Plastic SOIC (3.9 mm body), 14-lead = Plastic SOIC (3.9 mm body), 8-lead = Plastic TSSOP (4.4 mm body), 14-lead b)
(c) 2009 Microchip Technology Inc.
DS21668D-page 35
MCP6141/2/3/4
NOTES:
DS21668D-page 36
(c) 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2009 Microchip Technology Inc.
DS21668D-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS21668D-page 38
(c) 2009 Microchip Technology Inc.

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